The present invention relates to a method for forming a semiconductor device, more particularly, to a method for forming a semiconductor device including a buried gate structure.
Among semiconductor memory devices, a dynamic random access memory (DRAM) is constructed of a plurality of unit cells, each including a capacitor and a transistor. The capacitor is used to temporarily store data. The transistor is used to move data between a bit line and the capacitor according to a control signal using the characteristics of a semiconductor to change an electric conductivity according to an environment. The transistor is composed of three regions including a gate, a source, and a drain. Charge transfer occurs between the source and the drain according to a control signal input to the gate. The charge transfer between the source and the drain is achieved through a channel region using the characteristics of the semiconductor.
A typical transistor is manufactured on a semiconductor substrate. After a gate is formed on the semiconductor substrate, impurities are doped on both sides of the gate to form a source and a drain. In this case, a channel region of a transistor is formed between the source and the drain under the gate. The transistor having such a horizontal channel region occupies a predetermined area of a semiconductor substrate. In the case of a complicated semiconductor memory device, it becomes difficult to reduce a total area due to a plurality of transistors included therein.
When the total area of a semiconductor memory device is reduced, the number of semiconductor memory devices per wafer may be increased to enhance productivity. Various methods have been proposed to reduce the total area of the semiconductor memory device. Among them, one method uses a recess gate in which a recess is formed in a substrate and a gate is formed in the recess to form a channel region along a curve of the recess, instead of a conventional planar gate with a horizontal channel region. In addition to the recess gate, research into a buried gate has been made. In this case, an entire part of the gate is buried in the recess to form the buried gate.
Meanwhile, in order to form a semiconductor device with a buried gate according to the related art, a bit line of a cell region and a gate of a peripheral circuit region are simultaneously patterned.
In summary, after a bit line of a cell region and a gate of a peripheral circuit region are simultaneously patterned, an interlayer dielectric layer is deposited on the entire upper parts of the cell region and the peripheral circuit region to define a storage electrode contact. At this time, Boron Phosphorous Silicate Glass (BPSG) is used as an interlayer dielectric layer material to fill the space between the bit lines of the cell region. Here, a spacer is thickly formed over an upper part of the gate of the peripheral circuit region to prevent boron of the BPSG from permeating into a semiconductor substrate of the peripheral circuit region.
However, in this procedure, the spacer at an upper part and a sidewall of a bit line in the cell region is also thickly formed as well. This reduces a contact area between an active region and a storage electrode contact, and thus increases resistance. Furthermore, when the BPSG is applied as the interlay dielectric layer, a thermal process should be essentially performed. This causes a problem where a gate operation current of the peripheral circuit region is decreased and a leakage current is increased. Moreover, when a storage electrode is formed in the cell region, a hard mask layer (over the bit line in the cell region) is thickly formed as an etch stopping layer. In the same manner, a gate formed in the peripheral circuit region also turns out to have a thick hard mask. A gate pattern and a storage electrode pattern with a high aspect ratio makes it hard to properly adjust a tiling angle during an implant process.